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LT3957A 1 3957af n wide input voltage range: 3v to 40v n single feedback pin for positive or negative output voltage n internal 5a/40v power switch n current mode control provides excellent transient response n programmable operating frequency (100khz to 1mhz) with one external resistor n synchronizable to an external clock n low shutdown current < 1a n internal 5.2v low dropout voltage regulator n programmable input undervoltage lockout with hysteresis n programmable soft-start n thermally enhanced qfn (5mm 6mm) package typical application description boost, flyback, sepic and inverting converter with 5a, 40v switch the lt ? 3957a is a wide input range, current mode dc/dc converter which is capable of generating either positive or negative output voltages. it can be configured as either a boost, flyback, sepic or inverting converter. it features an internal low side n-channel power mosfet rated for 40v at 5a and driven from an internal regulated 5.2v supply. the fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. the operating frequency of LT3957A can be set with an external resistor over a 100khz to 1mhz range, and can be synchronized to an external clock using the sync pin. a minimum operating supply voltage of 3v, and a low shutdown quiescent current of less than 1a, make the LT3957A ideally suited for battery-powered systems. the LT3957A features soft-start and frequency foldback functions to limit inductor current during start-up. the LT3957A has improved load transient performance com- pared to the lt3957. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7825665. high efficiency output boost converter features applications n automotive n telecom n industrial efficiency vs output current sense2 sense1 LT3957A 10h v in sw gnd fbx rt ss intv cc en/uvlo sync sgnd 95.3k v c 3957a ta01a 200k 41.2k 300khz 4.7f 0.33f 6.8k 22nf 226k 15.8k 10f 2 v out 24v 600ma v in 4.5v to 16v 10f output current (ma) 0 70 efficiency (%) 75 80 85 90 95 100 100 200 300 400 500 3957a ta01b 600 v in = 12v http://www..net/ datasheet pdf - http://www..net/
LT3957A 2 3957af pin configuration absolute maximum ratings v in , en / uvlo ( note 5), sw ...................................... 40 v intv cc ...................................................... v in + 0.3 v , 8 v sync .......................................................................... 8 v v c , ss ......................................................................... 3 v rt ............................................................................ 1.5 v sense 1, sgnd ................... internally connected to gnd sense 2 .................................................................. 0.3 v fbx ................................................................. C6 v to 6 v operating junction temperature range ( note 2) .................................................. C40 c to 125 c maximum junction temperature .......................... 125 c storage temperature range .................. C65 c to 125 c (note 1) 12 13 14 top view sgnd 37 sw 38 uhe package 36-lead (5mm 6mm) plastic qfn 15 16 17 36 35 34 33 32 31 30 21 23 24 25 27 28 8 6 4 3 2 1nc nc sense2 sgnd sense1 sw sw nc intv cc v in en/uvlo sgnd sgnd sw sw nc nc sync rt ss fbx v c gnd gnd gnd gnd gnd gnd 20 9 10 t jmax = 125c, ja = 42c/w, jc = 3c/w exposed pad (pin 37) is sgnd, must be soldered to sgnd plane exposed pad (pin 38) is sw, must be soldered to sw plane order information lead free finish tape and reel part marking* package description temperature range LT3957Aeuhe#pbf LT3957Aeuhe#trpbf 3957a 36-lead (5mm 6mm) plastic qfn C40c to 125c LT3957Aiuhe#pbf LT3957Aiuhe#trpbf 3957a 36-lead (5mm 6mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ http://www..net/ datasheet pdf - http://www..net/
LT3957A 3 3957af electrical characteristics the l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at t a t j = 25c. v in = 24v, en/uvlo = 24v, sense2 = 0v, unless otherwise noted. parameter conditions min typ max units v in operating range 3 40 v v in shutdown i q en/uvlo = 0v en/uvlo = 1.15v 0.1 1 6 a a v in operating i q v c = 0.3v, r t = 41.2k 1.7 2.3 ma v in operating i q with internal ldo disabled v c = 0.3v, r t = 41.2k, intv cc = 5.5v 350 400 a sw pin current limit l 5 5.9 6.8 a sw pin on voltage i sw = 3a 100 mv sense2 input bias current current out of pin C65 a error amplifier fbx regulation voltage (v fbx(reg) ) fbx > 0v (note 3) fbx < 0v (note 3) l l 1.569 C0.816 1.6 C0.800 1.631 C0.784 v v fbx overvoltage lockout fbx > 0v (note 4) fbx < 0v (note 4) 6 7 8 11 10 14 % % fbx pin input current fbx = 1.6v (note 3) fbx = C 0.8v (note 3) C10 70 100 10 na na transconductance g m (?i vc /?fbx) (note 3) 230 s v c output impedance (note 3) 5 m v fbx line regulation (?v fbx /[?v in ? v fbx(reg) ]) fbx > 0v, 3v < v in < 40v (notes 3, 6) fbx < 0v, 3v < v in < 40v (notes 3, 6) 0.04 0.03 0.06 0.06 %/ v %/ v v c current mode gain (?v vc /?v sense ) 10 v/ v v c source current v c = 1.5v, fbx = 0v, current out of pin C15 a v c sink current fbx = 1.7v fbx = C 0.85v 12 11 a a oscillator switching frequency r t = 140k to sgnd, fbx = 1.6 v , v c = 1.5 v r t = 41.2k to sgnd, fbx = 1.6 v , v c = 1.5 v r t = 10.5k to sgnd, fbx = 1.6 v , v c = 1.5 v 80 270 850 100 300 1000 120 330 1200 khz khz khz rt voltage fbx = 1.6v 1.2 v sw minimum off- time 220 275 ns sw minimum on- time 240 320 ns sync input low 0.4 sync input high 1.5 ss pull-up current ss = 0v, current out of pin C10 a low dropout regulator intv cc regulation voltage l 5 5.2 5.45 v intv cc undervoltage lockout threshold falling intv cc uvlo hysteresis 2.6 2.7 0.15 2.85 v v http://www..net/ datasheet pdf - http://www..net/
LT3957A 4 3957af electrical characteristics the l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at t a t j = 25c. v in = 24v, en/uvlo = 24v, sense2 = 0v, unless otherwise noted. parameter conditions min typ max units intv cc current limit v in = 40v v in = 15v 32 40 95 55 ma ma intv cc load regulation (?v intvcc / v intvcc ) 0 < i intvcc < 20ma, v in = 8v C1 C0.5 % intv cc line regulation (?v intvcc / [?v in ? v intvcc ]) 6v < v in < 40v 0.02 0.05 %/ v dropout voltage (v in C v intvcc ) v in = 5v, i intvcc = 20ma, v c = 0v 450 mv intv cc current in shutdown en/uvlo = 0v, intv cc = 6v 17 a intv cc voltage to bypass internal ldo 5.5 v logic inputs en/uvlo threshold voltage falling v in = intv cc = 6v l 1.17 1.22 1.27 v en/uvlo voltage hysteresis 20 mv en/uvlo input low voltage i vin drops below 1a 0.4 v en/uvlo pin bias current low en/uvlo = 1.15v 1.7 2 2.5 a en/uvlo pin bias current high en/uvlo = 1.33v 20 100 na note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT3957Ae is guaranteed to meet performance specifications from the 0c to 125c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3957Ai is guaranteed over the full C40c to 125c operating junction temperature range. note 3: the LT3957A is tested in a feedback loop which servos v fbx to the reference voltages (1.6v and C 0.8v) with the v c pin forced to 1.3v. note 4: fbx overvoltage lockout is measured at v fbx( overvoltage) relative to regulated v fbx(reg) . note 5: for 3v v in < 6v, the en/uvlo pin must not exceed v in . note 6: en/uvlo = 1.33v when v in = 3v. typical performance characteristics positive feedback voltage vs temperature, v in negative feedback voltage vs temperature, v in quiescent current vs temperature, v in t a t j = 25c, unless otherwise noted. temperature (c) ?50 1580 regulated feedback voltage (mv) 1590 1600 1605 0 50 75 1585 ?25 25 100 125 3957a g01 v in = 40v v in = 24v v in = 8v v in = intv cc = 3v, shdn/uvlo = 1.33v temperature (c) ?50 ?804 regulated feedback voltage (mv) ?802 ?800 ?796 ?798 ?794 ?788 ?790 0 50 75 ?792 ?25 25 100 125 3957a g02 v in = 40v v in = 24v v in = 8v v in = intv cc = 3v shdn/uvlo = 1.33v temperature (c) ?50 1.4 quiescent current (ma) 1.6 1.8 0 50 75 1.5 1.7 ?25 25 100 125 3957a g03 v in = 40v v in = 24v v in = intv cc = 3v http://www..net/ datasheet pdf - http://www..net/
LT3957A 5 3957af typical performance characteristics t a t j = 25c, unless otherwise noted. dynamic quiescent current vs switching frequency r t vs switching frequency normalized switching frequency vs fbx switching frequency (khz) 100 0 i q (ma) 4 6 12 300 500 600 700 2 8 10 200 400 900800 1000 3957a g04 switching frequency (khz) 0 10 r t (k) 100 1000 300 500 600 700 100 200 400 900800 1000 3957a g05 fbx voltage (v) ?0.8 0 normalized frequency (%) 20 40 60 80 120 ?0.4 0 0.4 0.8 3957a g06 1.2 1.6 100 switching frequency vs temperature sw pin current limit vs temperature temperature (c) ?50 275 switching frequency (khz) 280 285 290 295 300 305 310 325 ?25 0 25 7550 3957a g07 100 125 315 320 r t = 41.2k temperature (c) ?50 5.4 sw pin current limit (a) 6.0 5.8 6.2 6.4 6.6 0 50 75 5.6 ?25 25 100 125 3957a g08 sw pin current limit vs duty cycle duty cycle (%) 0 5.4 5.6 5.8 sw pin current limit (a) 6.2 20 40 8060 6.6 6.0 6.4 100 3957a g09 en/uvlo threshold vs temperature en/uvlo current vs voltage en/uvlo hysteresis current vs temperature temperature (c) ?50 1.18 1.22 1.24 1.28 0 50 75 1.20 ?25 25 100 125 1.26 3957a g10 en/uvlo voltage (v) en/uvlo rising en/uvlo falling en/uvlo voltage (v) 0 0 en/uvlo current (a) 20 10 30 20 40 10 30 40 3957a g11 temperature (c) ?50 1.6 i en/uvlo (a) 1.8 2.0 2.2 2.4 0 50 75 ?25 25 100 125 3957a g12 http://www..net/ datasheet pdf - http://www..net/
LT3957A 6 3957af intv cc line regulation intv cc dropout voltage vs current, temperature intv cc vs temperature intv cc minimum output current limit vs v in intv cc load regulation typical performance characteristics t a t j = 25c, unless otherwise noted. temperature (c) ?50 5.0 intv cc (v) 5.1 5.2 5.3 5.4 0 50 75 ?25 25 100 125 3957a g13 1 0 10 20 40 60 10 100 90 80 30 50 70 t j = 125c intv cc = 3v v in (v) 3957a g14 intv cc current (ma) intv cc load (ma) 0 4.8 5.0 5.1 5.2 5.3 30 50 60 4.9 10 20 40 3957a g15 intv cc voltage (v) v in = 6v v in (v) 0 intv cc voltage (v) 5.25 5.20 10 15 25 5 20 30 35 40 5.15 5.10 5.30 3957a g16 intv cc load (ma) 0 dropout voltage (mv) 600 400 500 200 300 5 10 15 20 100 0 700 3957a g17 125c 25c 0c ?40c 75c v in = 5v internal switch on-resistance vs temperature temperature (c) ?50 on-resistance (m) 35 40 45 30 25 ?25 250 50 75 100 125 10 5 0 20 50 15 3957a g18 internal switch on-resistance vs intv cc sepic typical start-up waveforms sepic fbx frequency foldback waveforms during overcurrent intv cc (v) 3 on-resistance (m) 27.8 28.0 27.6 27.4 27.2 4 5 76 8 27.0 26.8 26.6 28.2 3957a g19 5ms/div see typical application: 5v to 16v input, 12v output sepic converter v out 5v/div i l1a + i l1b 2a/div 3957a g20 v in = 12v 50s/div v out 10v/div v sw 20v/div i l1a + i l1b 5a/div 3957a g21 v in = 12v see typical application: 5v to 16v input, 12v output sepic converter http://www..net/ datasheet pdf - http://www..net/
LT3957A 7 3957af pin functions nc (pins 1, 2, 10, 35, 36): no internal connection. leave these pins open or connect them to the adjacent pins. sense2 (pin 3): the current sense input for the control loop. connect this pin to sense1 pin directly or through a low pass filter (connect this pin to sense1 pin through a resistor, and to sgnd through a capacitor). sgnd (pins 4, 23, 24, exposed pad pin 37): signal ground. all small-signal components should connect to this ground. sgnd is connected to gnd inside the ic to ensure kelvin connection for the internal switch current sensing. do not connect sgnd and gnd externally. sense 1 (pin 6): the current sense output of the inter - nal n-channel mosfet. connect this pin to sense2 pin directly or through a lowpass filter (connect this pin to sense1 pin through a resistor, then connect sense2 to sgnd through a capacitor). sw (pins 8, 9, 20, 21, exposed pad pin 38): drain of internal power n-channel mosfet. gnd (pins 12, 13, 14, 15, 16, 17): ground. these pins connect to the source terminal of internal power n - channel mosfet through an internal sense resistor. gnd is con- nected to sgnd inside the ic to ensure kelvin connection for the internal switch current sensing. do not connect gnd and sgnd externally. en/uvlo (pin 25): shutdown and undervoltage detect pin. an accurate 1.22v (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2a pull-down current. an undervoltage condition resets soft-start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. v in ( pin 27): input supply pin. the v in pin can be locally bypassed with a capacitor to gnd (not sgnd). intv cc (pin 28): regulated supply for internal loads and gate driver. supplied from v in and regulated to 5.2v (typical). intv cc must be bypassed to sgnd with a minimum of 4.7f capacitor placed close to pin. intv cc can be connected directly to v in , if v in is less than 8v . intv cc can also be connected to a power supply whose voltage is higher than 5.5v, and lower than v in , provided that supply does not exceed 8v . v c (pin 30): error amplifier compensation pin. used to stabilize the voltage loop with an external rc network . place compensation components between the v c pin and sgnd . fbx (pin 31): positive and negative feedback pin. re- ceives the feedback voltage from the external resistor divider between the output and sgnd. also modulates the switching frequency during start-up and fault conditions when fbx is close to sgnd. ss (pin 32): soft-start pin. this pin modulates compen- sation pin voltage (v c ) clamp. the soft-start interval is set with an external capacitor between ss pin and sgnd. the pin has a 10a (typical) pull-up current source to an internal 2.5v rail. the soft-start pin is reset to sgnd by an undervoltage condition at en/uvlo, an intv cc undervolt - age or overvoltage condition or an internal thermal lockout . rt (pin 33): switching frequency adjustment pin. set the frequency using a resistor to sgnd. do not leave this pin open. sync (pin 34): frequency synchronization pin. used to synchronize the switching frequency to an outside clock. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than the sync pulse frequency. tie the sync pin to sgnd if this feature is not used. sync is bypassed when fbx is close to sgnd. http://www..net/ datasheet pdf - http://www..net/
LT3957A 8 3957af block diagram figure 1. LT3957A block diagram working as a sepic converter l1 r3r4 l2 1.22v 2.5v d1 c dc c in v out c out c vcc intv cc sense1 gnd sense2 m2 v in r sense m1 v isense ? v in i s1 2a 27 sw 28 12, 13, 14, 15, 16, 17 25 en/uvlo internal regulator and uvlo tlo 165?c a10 q3 v c 2.7v a8 uvlo i s2 10a i s3 driver slope sense 48mv sr1 + ? current limit ramp generator 5.2v ldo ? + ? r o s 2.5v rt r t ss c ss sync 1.28v 1.2v 1.6v ?0.8v + ? + ? + ? 32 v c 30 fbx 31 34 33 sgnd 4, 23, 24, 37 + ? + ? 6 3 ramp pwm comparator frequency foldback 100khz-1mhz oscillator freq prog c c2 c c1 3957a f01 ? + + q1 a1 a2 1.72v ?0.88v + ? + ? a11 a12 a3 a4 a5 a6 g2 g5 g6 a7 q2 g4 8, 9, 20, 21, 38 r1 r2 v out r c g1 http://www..net/ datasheet pdf - http://www..net/
LT3957A 9 3957af applications information main control loop the LT3957A uses a fixed frequency, current mode con- trol scheme to provide excellent line and load regulation. operation can be best understood by referring to the block diagram in figure 1. the start of each oscillator cycle sets the sr latch (sr1) and turns on the internal power mosfet switch m 1 through driver g2. the switch current flows through the internal current sensing resistor r sense and generates a voltage proportional to the switch current. this current sense voltage v isense (amplified by a5) is added to a stabilizing slope compensation ramp and the resulting sum (slope) is fed into the positive terminal of the pwm comparator a7. when slope exceeds the level at the negative input of a7 (v c pin), sr1 is reset, turning off the power switch. the level at the negative input of a7 is set by the error amplifier a1 (or a2) and is an amplified version of the difference between the feedback voltage (fbx pin) and the reference voltage (1.6v or C0.8v, depending on the configuration). in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the LT3957A has a switch current limit function. the cur - rent sense voltage is input to the current limit comparator a6. if the sense2 pin voltage is higher than the sense current limit threshold v sense(max) (48 mv, typical), a6 will reset sr1 and turn off m1 immediately. the LT3957A is capable of generating either positive or negative output voltage with a single fbx pin. it can be configured as a boost, flyback or sepic converter to gen- erate positive output voltage, or as an inverting converter to generate negative output voltage. when configured as a sepic converter, as shown in figure 1, the fbx pin is pulled up to the internal bias voltage of 1.6v by a volt- age divider (r1 and r2) connected from v out to sgnd. comparator a2 becomes inactive and comparator a1 performs the inverting amplification from fbx to v c . when the LT3957A is in an inverting configuration, the fbx pin is pulled down to C0.8v by a voltage divider connected from v out to sgnd. comparator a1 becomes inactive and comparator a2 performs the noninverting amplification from fbx to v c . the LT3957A has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start- up or recovery from a short- circuit condition. an overvoltage comparator a11 (with 20mv hysteresis) senses when the fbx pin voltage exceeds the positive regulated voltage (1.6v) by 8% and provides a reset pulse. similarly, an overvoltage comparator a12 (with 10mv hysteresis) senses when the fbx pin voltage exceeds the negative regulated voltage (C0.8v) by 11% and provides a reset pulse. both reset pulses are sent to the main rs latch (sr1) through g6 and g5. the power mosfet switch m1 is actively held off for the duration of an output overvoltage condition. programming turn-on and turn-off thresholds with the en/uvlo pin the en/ uvlo pin controls whether the LT3957A is enabled or is in shutdown state. a micropower 1.22v reference, a comparator a10 and a controllable current source i s1 allow the user to accurately program the supply voltage at which the ic turns on and off. the falling value can be accurately set by the resistor dividers r3 and r4. when en / uvlo is above 0.4 v , and below the 1.22 v threshold , the small pull-down current source i s1 ( typical 2a) is active. the purpose of this current is to allow the user to program the rising hysteresis . the block diagram of the comparator and the external resistors is shown in figure 1. the typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: v vin,falling = 1.22 ? (r3 + r4) r4 v vin,rising = 2a ? r3 + v in,falling for applications where the en/uvlo pin is only used as a logic input, the en/uvlo pin can be connected directly to the input voltage v in for always-on operation. http://www..net/ datasheet pdf - http://www..net/
LT3957A 10 3957af applications information intv cc regulator bypassing and operation an internal, low dropout (ldo) voltage regulator produces the 5.2v intv cc supply which powers the gate driver, as shown in figure 1. the LT3957A contains an undervoltage lockout comparator a8 for the intv cc supply. the intv cc undervoltage ( uv) threshold is 2.7v (typical), with 0.1v hysteresis, to ensure that the internal mosfet has suf- ficient gate drive voltage before turning on. when intv cc is below the uv threshold, the internal power switch will be turned off and the soft-start operation will be triggered. the logic circuitry within the LT3957A is also powered from the internal intv cc supply. the intv cc regulator must be bypassed to sgnd imme- diately adjacent to the ic pins with a minimum of 4.7f ceramic capacitor. good bypassing is necessary to sup- ply the high transient currents required by the mosfet gate driver. in an actual application, most of the ic supply current is used to drive the gate capacitance of the internal power mosfet. the on-chip power dissipation can be significant when the internal power mosfet is being driven at a high frequency and the v in voltage is high. an effective approach to reduce the power consumption of the internal ldo for gate drive and to improve the efficiency is to tie the intv cc pin to an external voltage source high enough to turn off the internal ldo regulator. in sepic or flyback applications, the intv cc pin can be connected to the output voltage v out through a blocking diode, as shown in figure 2, if v out meets the following conditions: 1. v out < v in (pin voltage) 2. v out < 8v a resistor r vcc can be connected, as shown in figure 2, to limit the inrush current from v out . regardless of whether or not the intv cc pin is connected to an external voltage source , it is always necessary to have the driver circuitry bypassed with a 4.7 f low esr ceramic capacitor to ground immediately adjacent to the intv cc and sgnd pins. if LT3957A operates at a low v in and high switching fre- quency, the voltage drop across the drain and the source of the ldo pmos (m2 in figure 1) could push intv cc to be below the uv threshold . to prevent this from happening , the intv cc pin can be shorted directly to the v in pin. v in must not exceed the intv cc absolute maximum rating (8v). in this condition, the internal ldo will be turned off and the gate driver will be powered directly from v in . it is recommended that intv cc pin be shorted to the v in pin if v in is lower than 3.5v at 1mhz switching frequency, or v in is lower than 3.2v at 100khz switching frequency. with the intv cc pin shorted to v in , however, a small current (around 16a) will load the intv cc in shutdown mode. figure 2. connecting intv cc to v out c vcc 4.7f v out 3957a f02 intv cc sgnd LT3957A r vcc d vcc http://www..net/ datasheet pdf - http://www..net/
LT3957A 11 3957af applications information operating frequency and synchronization the choice of operating frequency may be determined by on-chip power dissipation (a low switching frequency may be required to ensure ic junction temperature does not exceed 125c), otherwise it is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing gate drive current and mosfet and diode switching losses. however, lower frequency operation requires a physically larger induc- tor. switching frequency also has implications for loop compensation. the LT3957A uses a constant-frequency architecture that can be programmed over a 100khz to 1000khz range with a single external resistor from the rt pin to sgnd, as shown in figure 1. a table for selecting the value of r t for a given operating frequency is shown in table 1. table 1. timing resistor (r t ) value switching frequency (khz) r t (k) 100 140 200 63.4 300 41.2 400 30.9 500 24.3 600 19.6 700 16.5 800 14 900 12.1 1000 10.5 the operating frequency of the LT3957A can be synchro- nized to an external clock source . by providing a digital clock signal into the sync pin, the LT3957A will operate at the sync clock frequency. the LT3957A detects the rising edge of each clock cycle . if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. it is recommended that the sync pin has a minimum pulse width of 200ns. tie the sync pin to sgnd if this feature is not used. duty cycle consideration switching duty cycle is a key variable defining converter operation . as such , its limits must be considered . minimum on-time is the smallest time duration that the LT3957A is capable of turning on the power mosfet. this time is typically about 240ns (see minimum on- time in the electrical characteristics table). in each switching cycle, the LT3957A keeps the power switch off for at least 220ns (typical ) (see minimum off- time in the electrical characteristics table). the minimum on - time , minimum off - time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: minimum duty cycle = minimum on-time ? frequency maximum duty cycle = 1 C ( minimum off- time ? frequency) programming the output voltage the output voltage v out is set by a resistor divider, as shown in figure 1. the positive and negative v out are set by the following equations: v out,positive = 1.6v s 1+ r2 r1 ? ? ? ? ? ? v out,negative = ?0.8v s 1+ r2 r1 ? ? ? ? ? ? the resistors r1 and r2 are typically chosen so that the error caused by the current flowing into the fbx pin during normal operation is less than 1% (this translates to a maximum value of r1 at about 158k). http://www..net/ datasheet pdf - http://www..net/
LT3957A 12 3957af applications information soft-start the LT3957A contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible , resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the LT3957A addresses this mechanism with the ss pin. as shown in figure 1, the ss pin reduces the power mosfet current by pulling down the v c pin through q2. in this way the ss allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. the typical start-up waveforms are shown in the typical performance characteristics section. the inductor current i l slewing rate is limited by the soft-start function. besides start-up (with en/uvlo), soft-start can also be triggered by the following faults: 1. intv cc < 2.85v 2. thermal lockout (tlo > 165c) any of these three faults will cause the LT3957A to stop switching immediately. the ss pin will be discharged by q3. when all faults are cleared and the ss pin has been discharged below 0.2v, a 10a current source i s2 starts charging the ss pin, initiating a soft-start operation. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 1.25v 10a fbx frequency foldback when v out is very low during start-up, or an output short- circuit on a sepic, an inverting, or a flyback converter, the switching regulator must operate at low duty cycles to keep the power switch current below the current limit, since the inductor current decay rate is very low during switch off time. the minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. so, the switch current may keep increasing through each switch cycle, exceeding the programmed current limit. to prevent the switch peak currents from exceeding the programmed value , the lt3957 a contains a frequency foldback function to reduce the switching frequency when the fbx voltage is low (see the normalized switching frequency vs fbx graph in the typical performance characteristics section). during frequency foldback, external clock synchroniza- tion is disabled to prevent interference with frequency reducing operation. loop compensation loop compensation determines the stability and transient performance . the LT3957A uses current mode control to regulate the output which simplifies loop compensation. the LT3957A improves the no-load to heavy load transient response, compared to the lt3957. new internal circuits ensure that the transition from not switching to switching at high current can be made in a few cycles. the optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). to compensate the feedback loop of the LT3957A, a series resistor-capacitor network is usually connected from the v c pin to sgnd. figure 1 shows the typical v c compensation network. for most applications, the capacitor should be in the range of 470pf to 22nf, and the resistor should be in the range of 5k to 50k. a small capacitor is often connected in parallel with the rc compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 10pf to 100pf. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance . stability should then be checked across all operating conditions, including load current, input voltage and temperature. application note 76 is a good reference on loop compensation. http://www..net/ datasheet pdf - http://www..net/
LT3957A 13 3957af applications information the internal power switch current for control and protection, the LT3957A measures the internal power mosfet current by using a sense resistor (r sense ) between gnd and the mosfet source . figure 3 shows a typical waveform of the internal switch current (i sw ). due to the current limit ( minimum 5 a ) of the internal power switch, the LT3957A should be used in the applications that the switch peak current i sw(peak) during steady state normal operation is lower than 5a by a sufficient margin (10% or higher is recommended). the LT3957A switching controller incorporates 100ns timing interval to blank the ringing on the current sense signal across r sense immediately after m1 is turned on. this ringing is caused by the parasitic inductance and capacitance of the pcb trace, the sense resistor, the diode, and the mosfet. the 100ns timing interval is adequate for most of the LT3957A applications. in the applications that have very large and long ringing on the current sense signal, a small rc filter can be added to filter out the excess ringing. figure 4 shows the rc filter on the sense1 and sense2 pins. it is usually sufficient to choose 22 for r f lt and 2.2nf to 10nf for c flt . keep r f lt s resistance low. remember that there is 65a (typical) flowing out of the sense2 pin. adding r f lt will affect the internal power switch current limit threshold: i sw _ilim = 1 ? 65a ? r flt 48mv ? ? ? ? ? ? ? 5a on- chip power dissipation and thermal lockout ( tlo) the on- chip power dissipation of LT3957A can be estimated using the following equation: p ic i 2 sw t d tr ds(on) + v 2 peak t i sw t ? tpf/a + v in tma + ?tnc) where r ds(on) is the internal switch on-resistance which can be obtained from the typical performance characteris - tics section. v sw(peak) is the peak switch off-state voltage. the maximum power dissipation p ic(max) can be obtained by comparing p ic across all the v in range at the maximum output current . the highest junction temperature can be estimated using the following equation: t j(max) t a + p ic(max) tc/w it is recommended to measure the ic temperature in steady state to verify that the junction temperature limit is not exceeded. a low switching frequency may be required to ensure t j(max) does not exceed 125c. if lt 3957 a die temperature reaches thermal lockout threshold at 165c (typical), the ic will initiate several protective actions. the power switch will be turned off. a soft-start operation will be triggered. the ic will be en- abled again when the junction temperature has dropped by 5c (nominal). figure 3. the switch current during a switching cycle 3957a f03 i sw(peak) ?i sw i sw t dt s t s figure 4. the rc filter on sense1 pin and sense2 pin 3957a f04 LT3957A r flt c flt sense2 sgnd sense1 http://www..net/ datasheet pdf - http://www..net/
LT3957A 14 3957af applications information application circuits the lt 3957 a can be configured as different topologies . the first topology to be analyzed will be the boost converter, followed by the flyback, sepic and inverting converters. boost converter: switch duty cycle and frequency the LT3957A can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost converters are not short - circuit protected . under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short- circuit protected, please refer to the applications information section covering sepic converters. the conversion ratio as a function of duty cycle is v out v in = 1 1? d in continuous conduction mode (ccm). for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out discontinuous conduction mode (dcm) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. boost converter: maximum output current capability and inductor selection for the boost topology, the maximum average inductor current is: i l(max) = i o(max) ? 1 1? d max due to the current limit of its internal power switch, the LT3957A should be used in a boost converter whose maxi- mum output current (i o(max) ) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): i o(max) < v in(min) v out ? 5a ? 0.5 ? ? i sw ( ) the inductor ripple current ?i sw has a direct effect on the choice of the inductor value and the converters maximum output current capability. choosing smaller values of ?i sw increases output current capability, but requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i sw provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses, and reduces output current capability. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: l = v in(min) ? i sw ? ? ? d max the peak inductor current is the switch current limit (5.9a typical), and the rms inductor current is approximately equal to i l(max) . the user should choose the inductors having sufficient saturation and rms current ratings. boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. the average forward current in normal operation is equal to the output current. it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out by a safety margin (a 10v safety margin is usually sufficient). http://www..net/ datasheet pdf - http://www..net/
LT3957A 15 3957af applications information the power dissipated by the diode is: p d = i o(max) ? v d where v d is diodes forward voltage drop, and the diode junction temperature is: t j = t a + p d ? r ja the r ja to be used in this equation normally includes the r jc for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating . boost converter: output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters ( esr, esl and bulk c ) on the output voltage ripple waveform for a typical boost converter is illustrated in figure 5. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step ?v esr and the charging/discharg- ing ?v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ?v esr and ?v cout . this percentage ripple will change, depending on the requirements of the application, and the following equations can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr cout 0.01 s v out i d(peak) for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 s v out s ? the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 5. the rms ripple current rating of the output capacitor can be determined using the following equation: i rms(cout) i o(max) s d max 1? d max multiple capacitors are often paralleled to meet esr requirements. typically , once the esr requirement is satisfied, the capacitance is adequate for filtering and has the required rms current rating . additional ceramic capaci - tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor , which reduces high frequency switching noise on the converter output. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current wave- form is continuous. the input voltage source impedance determines the size of the input capacitor, which is typi- cally in the range of 1f to 100f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i rms(cin) = 0.3 ? ?i l figure 5. the output ripple waveform of a boost converter v out (ac) t on ?v esr ringing due to total inductance (board + cap) ?v cout 3957a f05 t off http://www..net/ datasheet pdf - http://www..net/
LT3957A 16 3957af applications information figure 7 shows the waveforms of the flyback converter in discontinuous mode operation. during each switching period t s , three subintervals occur: dt s , d2t s , d3t s . during dt s , m is on, and d is reverse-biased. during d2t s , m is off, and l s is conducting current. both l p and l s currents are zero during d3t s . flyback converter applications the lt3957 a can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. due to the 40v rating of the internal power switch, LT3957A should be used in low input voltage flyback converters. figure 6 shows a simplified flyback converter. the flyback converter has a very low parts count for mul- tiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. however, it has low efficiency due to the high peak currents , high peak voltages and consequent power loss. the flyback converter is commonly used for an output power of less than 50w. the flyback converter can be designed to operate either in continuous or discontinuous mode. compared to con- tinuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compen- sation, and the disadvantage of higher peak-to-average current and lower efficiency. figure 7. waveforms of the flyback converter in discontinuous mode operation 3957a f07 i sw v sw i d t dt s d2t s d3t s i sw(max) i d(max) t s figure 6. a simplified flyback converter n p :n s v in c in c sn v sn l p d suggested rcd snubber i d i sw 3957a f06 gnd sw LT3957A l s + ? r sn d sn + ? v out c out + + flyback converter: switch duty cycle and turns ratio the flyback converter conversion ratio in the continuous mode operation is: v out v in = n s n p ? d 1? d where n s /n p is the second to primary turns ratio. d is duty cycle. the flyback converter conversion ratio in the discontinu- ous mode operation is: v out v in = n s n p ? d d2 according to figure 6, the peak sw voltage is: v sw(peak) = v in(max) + v sn where v sn is the snubber capacitor voltage. a smaller v sn results in a larger snubber loss. a reasonable v sn is 1.5 to 2 times of the reflected output voltage: v sn = k ? v out ? n p n s k = 1.5 ~ 2 http://www..net/ datasheet pdf - http://www..net/
LT3957A 17 3957af applications information according to the absolute maximum ratings table , the sw voltage absolute maximum value is 40v. therefore, the maximum primary to secondary turns ratio (for both the continuous and the discontinuous operation) should be. n p n s 40v ? v in(max) k ? v out according to the preceding equations , the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. the selections of the duty cycle and the turns ratio are somewhat iterative processes, due to the number of variables involved. the user can choose either a duty cycle or a turns ratio as the start point. the following trade-offs should be considered when select- ing the switch duty cycle or turns ratio, to optimize the converter performance . a higher duty cycle affects the flyback converter in the following aspects: t lower mosfet rms current i sw(rms) , but higher mosfet v sw peak voltage t lower diode peak reverse voltage, but higher diode rms current i d(rms) t higher transformer turns ratio (n p /n s ) it is recommended to choose a duty cycle between 20% and 80%. flyback converter: maximum output current capability and transformer design the maximum output current capability and transformer design for continuous conduction mode (ccm) is chosen as presented here. the maximum duty cycle ( d max ) occurs when the converter has the minimum v in : d max = v out ? n p n s ? ? ? ? ? ? v out ? n p n s ? ? ? ? ? ? + v in(min) due to the current limit of its internal power switch, the LT3957A should be used in a flyback converter whose maximum output current ( i o ( max ) ) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): i o(max) < v in(min) v out ? d max ? 5a ? 0.5 ? ? i sw ( ) the transformer ripple current ?i sw has a direct effect on the design/choice of the transformer and the converters output current capability. choosing smaller values of ?i sw increases the output current capability, but requires large primary and secondary inductances and reduce the current loop gain (the converter will approach voltage mode). accepting larger values of ?i sw allows the use of low primary and secondary inductances, but results in higher input current ripple, greater core losses, and reduces the output current capability. given an operating input voltage range, and having chosen the operating frequency and ripple current in the primary winding , the primary winding inductance can be calculated using the following equation: l = v in(min) ? i sw ? ? ? d max the primary winding peak current is the switch current limit (typical 5.9a). the primary and secondary maximum rms currents are: i lp(rms) p out(max) d max ? v in(min) ? i ls(rms) i out(max) 1? d max where is the converter efficiency. based on the preceding equations, the user should design/ choose the transformer having sufficient saturation and rms current ratings. flyback converter: snubber design transformer leakage inductance (on either the primary or secondary ) causes a voltage spike to occur after the mosfet turn-off. this is increasingly prominent at higher http://www..net/ datasheet pdf - http://www..net/
LT3957A 18 3957af applications information load currents, where more stored energy must be dissi- pated. in some cases a snubber circuit will be required to avoid overvoltage breakdown at the mosfets drain node. there are different snubber circuits (such as rc snubber, rcd snubber, zener clamp, etc.), and application note 19 is a good reference on snubber design. an rc snubber circuit can be connected between sw and gnd to damp the ringing on sw pins . the snubber resistor values should be close to the impedance of the parasitic resonance. the snubber capacitor value should be larger than the circuit parasitic capacitance, but be small enough to keep the snubber resistor power dissipation low. if the rc snubber is insufficient to prevent sw pins over - voltage, the rcd snubber can be used to limit the peak voltage on the sw pins, which is shown in figure 6. the snubber resistor value (r sn ) can be calculated by the following equation: r sn = 2 ? v 2 sn ? v sn ? v out ? n p n s i 2 sw(peak) ? l lk ? ? l lk is the leakage inductance of the primary winding , w hich is usually specified in the transformer characteristics. l lk can be obtained by measuring the primary inductance with the secondary windings shorted. the snubber capacitor value ( c sn ) can be determined using the following equation: c cn = v sn ? v sn ? r sn ? ? where ?v sn is the voltage ripple across c sn . a reasonable ?v sn is 5% to 10% of v sn . the reverse voltage rating of d sn should be higher than the sum of v sn and v in(max) . a zener clamp can also be connected between sw and gnd to ensure sw voltage does not exceed 40v. flyback converter: output diode selection the output diode in a flyback converter is subject to large rms current and peak reverse voltage stresses. a fast switching diode with a low forward drop and a low reverse leakage is desired. schottky diodes are recommended if the output voltage is below 100v. approximate the required peak repetitive reverse voltage rating v rrm using: v rrm > n s n p ? v in(max) + v out the power dissipated by the diode is: p d = i o(max) tv d and the diode junction temperature is: t j = t a + p d tr ja the r ja to be used in this equation normally includes the r jc for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. flyback converter: output capacitor selection the output capacitor of the flyback converter has a similar operation condition as that of the boost converter. refer to the boost converter: output capacitor selection section for the calculation of c out and esr cout . the rms ripple current rating of the output capacitors in continuous operation can be determined using the following equation: i rms(cout),continuous i o(max) ? d max 1? d max flyback converter: input capacitor selection the input capacitor in a flyback converter is subject to a large rms current due to the discontinuous primary current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the rms ripple current rating of the input capacitors in continuous operation can be determined using the following equation: i rms(cin),continuous p out(max) v in(min) ? ? 1? d max d max http://www..net/ datasheet pdf - http://www..net/
LT3957A 19 3957af applications information sepic converter applications the LT3957A can be configured as a sepic (single-ended primary inductance converter), as shown in figure 1. this topology allows for the input to be higher, equal, or lower than the desired output voltage. the conversion ratio as a function of duty cycle is: v out + v d v in = d 1? d in continuous conduction mode (ccm). in a sepic converter, no dc path exists between the input and output. this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. compared to the flyback converter, the sepic converter has the advantage that both the power mosfet and the output diode voltages are clamped by the capacitors (c in , c dc and c out ), therefore, there is less voltage ringing across the power mosfet and the output diodes. the sepic converter requires much smaller input capacitors than those of the flyback converter. this is due to the fact that, in the sepic converter, the current through inductor l1 (which is series with the input) is continuous. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ), the input voltage (v in ) and the diode forward voltage (v d ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out + v d v in(min) + v out + v d sepic converter: the maximum output current capability and inductor selection as shown in figure 1, the sepic converter contains two inductors : l 1 and l 2. l 1 and l 2 can be independent , but can also be wound on the same core, since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max) = i in(max) = i o(max) ? d max 1 ? d max i l2(max) = i o(max) due to the current limit of its internal power switch, the LT3957A should be used in a sepic converter whose maximum output current (i o(max) ) is less than the output current capability by a sufficient margin (10% or higher is recommended): i o(max) < 1 ? d max ( ) ? 5a ? 0.5 ? ? i sw ( ) the inductor ripple currents ?i l1 and ?i l2 are identical: ?i l1 = ?i l2 t?i sw the inductor ripple current ?i sw has a direct effect on the choice of the inductor value and the converters maximum output current capability . choosing smaller values of ?i sw requires large inductances and reduces the current loop gain ( the converter will approach voltage mode). accepting larger values of ?i sw allows the use of low inductances, but results in higher input current ripple and greater core losses and reduces output current capability. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value ( l 1 and l 2 are independent ) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? ? i sw ? ? ? d max for most sepic applications, the equal inductor values will fall in the range of 1h to 100h. http://www..net/ datasheet pdf - http://www..net/
LT3957A 20 3957af applications information by making l 1 = l 2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) ? i sw ? ? ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) t?i l1 i l2(peak) = i l2(max) t?i l2 the maximum rms inductor currents are approximately equal to the maximum average inductor currents. based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur - rent ratings. sepic converter: output diode selection to maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. the average forward current in normal operation is equal to the output current. it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max) tv d where v d is diodes forward voltage drop, and the diode junction temperature is: t j = t a + p d tr ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter . please refer to the boost converter: output capacitor selection and boost converter: input capacitor selection sections. sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 1) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately C i o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . inverting converter applications the lt3957 a can be configured as a dual - inductor inverting topology, as shown in figure 8. the v out to v in ratio is: v out ? v d v in = ? d 1? d in continuous conduction mode (ccm). figure 8. a simplified inverting converter c dc v in c in l1 d1 c out v out 3757a f08 + gnd LT3957A sw l2 + ? + ? + http://www..net/ datasheet pdf - http://www..net/
LT3957A 21 3957af applications information inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage (v out ) and the input voltage (v in ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out ? v d v out ? v d ? v in(min) inverting converter: output diode and input capacitor selections the selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections. inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost, flyback and sepic converters for similar output ripples. this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: ? v out(p ? p) = ? i l2 ? esr cout + 1 8 ? ? ? c out ? ? ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt- age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) t?i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 10) should be larger than the maximum input voltage minus the output voltage (negative voltage): v cdc > v in(max) C v out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately C i o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1? d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . board layout the high power and high speed operation of the LT3957A demands careful attention to board layout and component placement. careful attention must be paid to the internal power dissipation of the LT3957A at high input voltages, high switching frequencies , and high internal power switch currents to ensure that a junction temperature of 125c is not exceeded. this is especially important when operat- ing at high ambient temperatures. exposed pads on the bottom of the package are sgnd and sw terminals of the ic, and must be soldered to a sgnd ground plane and a sw plane respectively. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into the copper planes with as much area as possible. to prevent radiation and high frequency resonance prob- lems, proper layout of the components connected to the ic is essential, especially the power paths with higher di/ dt. the following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: t in boost configuration, the high di/dt loop contains the output capacitor, the internal power mosfet and the schottky diode. http://www..net/ datasheet pdf - http://www..net/
LT3957A 22 3957af applications information ? in flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the internal power mosfet. the high di/dt secondary loop contains the output capacitor, the secondary winding and the output diode. ? in sepic configuration, the high di/dt loop contains the internal power mosfet, output capacitor, schottky diode and the coupling capacitor. ? in inverting configuration, the high di/dt loop contains internal power mosfet , schottky diode and the coupling capacitor. check the stress on the internal power mosfet by measuring the sw-to-gnd voltage directly across the ic terminals . make sure the inductive ringing does not exceed the maximum rating of the internal power mosfet (40v). the small-signal components should be placed away from high frequency switching nodes. for optimum load regulation and true remote sensing, the top of the output voltage sensing resistor divider should connect indepen- dently to the top of the output capacitor (kelvin connec- tion), staying away from any high dv/dt traces. place the divider resistors near the LT3957A in order to keep the high impedance fbx node short. figure 9 shows the suggested layout of the 4.5v to 16v input, 24v output boost converter in the typical applica- tion section. 3958a f09 LT3957A 37 38 12 13 14 15 16 17 36 35 34 33 32 31 30 21 23 24 25 27 28 8 6 4 3 2 1 20 9 10 via to v out r1 r2 c ss r t r c c c c vcc r3 r4 d1 l1 c out c out c in gnd v out v in via to v out vias to sgnd ground plane vias to sw plane figure 9. suggested layout of the 4.5v to 16v input. 24v output boost converter in the typical application section http://www..net/ datasheet pdf - http://www..net/
LT3957A 23 3957af applications information table 2. recommended component manufacturers vendor components web address avx capacitors avx.com bh electronics inductors, transformers bhelectronics.com coilcraft inductors coilcraft.com cooper bussmann inductors bussmann.com diodes, inc diodes diodes.com general semiconductor diodes generalsemiconductor. com international rectifier diodes irf .com kemet tantalum capacitors kemet.com magnetics inc toroid cores mag-inc.com microsemi diodes microsemi.com murata-erie inductors, capacitors murata.co.jp nichicon capacitors nichicon.com on semiconductor diodes onsemi.com panasonic capacitors panasonic.com pulse inductors pulseeng.com sanyo capacitors sanyo.co.jp sumida inductors sumida.com taiyo yuden capacitors t-yuden .com tdk capacitors, inductors component.tdk.com thermalloy heat sinks aavidthermalloy.com tokin capacitors nec- tokinamerica. com toko inductors tokoam.com united chemi-con capacitors chemi-com.com vishay inductors vishay.com w rth elektronik inductors we-online.com vishay/sprague capacitors vishay.com zetex small-signal discretes zetex.com recommended component manufacturers some of the recommended component manufacturers are listed in table 2. http://www..net/ datasheet pdf - http://www..net/
LT3957A 24 3957af typical applications 4.5v to 16v input, 24v output boost converter efficiency vs output current sense2 sense1 LT3957A l1 10h v in sw gnd fbx rt ss intv cc en/uvlo sync sgnd r4 95.3k v c 3957a ta02a d1 r3 200k r t 41.2k 300khz c vcc 4.7f 10v x5r c ss 0.33f r c 6.8k c c 22nf r2 226k r1 15.8k c out 10f 50v x5r 2 v out 24v 600ma v in 4.5v to 16v c in 10f 25v x5r c in : murata grm31er61h106ka12 c out : taiyo yuden umk325bj106mm d1: vishay siliconix 10bq040 l1: vishay siliconix ihlp-5050ce-1 output current (ma) 0 70 efficiency (%) 75 80 85 90 95 100 100 200 300 400 500 3957a ta02b 600 v in = 12v http://www..net/ datasheet pdf - http://www..net/
LT3957A 25 3957af typical applications 5v to 16v input, 12v output sepic converter efficiency vs output current load step waveforms start-up waveforms frequency foldback waveforms when output short-circuit sense2 sense1 LT3957A l1a l1b v in sw gnd fbx rt ss intv cc en/uvlo sync sgnd 82.5k v c 3957a ta03a d1 200k 41.2k 300khz c vcc 4.7f 10v x5r 0.47f 10k 10nf 105k 15.8k c dc 4.7f, 25v x5r v out 12v 1a v in 5v to 16v c in 4.7f 25v x5r c out 22f 16v x5r 2 ? ? c in , c dc : murata grm21br61e475ka12l c out : murata grm32er61c226ke20 d1: vishay siliconix 30bq040 l1a, l1b: coiltronics drq127-100 output current (ma) 0 50 efficiency (%) 65 60 55 70 75 80 85 90 95 100 200 400 600 800 3957a ta03b 1000 v in = 12v 5ms/div v out 5v/div i l1a + i l1b 2a/div 3957a ta03d v in = 12v 50s/div v out 10v/div v sw 20v/div i l1a + i l1b 5a/div 3957a ta03e v in = 12v 2ms/div v out 1v/div (ac) i out 0.5a/div 1a 0a 3957 ta03c v in = 12v http://www..net/ datasheet pdf - http://www..net/
LT3957A 26 3957af typical applications 5v to 16v input, C12v output inverting converter efficiency vs output current load step waveforms start-up waveforms frequency foldback waveforms when output short-circuit sense2 sense1 LT3957A l1a l1b v in sw gnd fbx rt ss intv cc en/uvlo sync sgnd 82.5k v c 395a7 ta04a d1 200k 41.2k 300khz c vcc 4.7f 10v x5r 0.47f 10k 10nf 105k 7.5k c dc 4.7f, 50v x7r v out ?12v 1a v in 5v to 16v c in 4.7f 25v x5r c out 22f 16v x5r 2 ? ? c in : murata grm21br61e475ka12l c dc : taiyo yuden umk316bj475kl c out : murata grm32er61c226ke20 d1: vishay siliconix 30bq040 l1a, l1b: coiltronics drq127-100 output current (ma) 0 50 efficiency (%) 65 60 55 70 75 80 85 90 95 100 200 400 600 800 3957a ta04b 1000 v in = 12v 5ms/div v out 5v/div i l1a + i l1b 2a/div 3957a ta04d v in = 12v 50s/div v out 10v/div v sw 20v/div i l1a + i l1b 5a/div 3957a ta04e v in = 12v 2ms/div v out 1v/div (ac) i out 0.2a/div 0.6a 0a 3957a ta04c v in = 12v http://www..net/ datasheet pdf - http://www..net/
LT3957A 27 3957af information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 6.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 1 3635 30 31 32 33 34 28 20 21 23 24 25 27 2 3 4 6 8 9 10 121314151617 bottom view?exposed pad 2.00 ref 1.50 ref 0.75 0.05 r = 0.125 typ r = 0.10 typ pin 1 notch r = 0.30 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uhe36(28)ma) qfn 0112 rev d recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.10 0.05 5.50 0.05 package outline 1.88 0.10 1.53 0.10 2.00 ref 1.50 ref 5.10 0.05 6.50 0.05 uhe package variation: uhe36(28)ma 36(28)-lead plastic qfn (5mm 6mm) (reference ltc dwg # 05-08-1836 rev d) 3.00 0.10 3.00 0.10 0.12 0.10 1.88 0.05 1.53 0.05 3.00 0.05 3.00 0.05 0.48 0.05 0.12 0.05 0.48 0.10 0.25 0.05 0.50 bsc 10 1 2 3 4 6 8 9 17 2021 232425 2728 30 31 32 33 34 35 36 12 13 14 15 16 http://www..net/ datasheet pdf - http://www..net/
LT3957A 28 3957af linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0312 ? printed in usa typical application part number description comments lt3957 boost, flyback, sepic and inverting converter with 5a/40v switch 3v v in 40v , current mode control, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn-36 package lt3958 high input voltage, boost, flyback, sepic and inverting converter with 3.5a/80v switch 5v v in < 80v , current mode control, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn-36 package lt3757 boost, flyback, sepic and inverting controller 2.9v v in 40v, current mode control, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e package lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, current mode control, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e package lt3759 boost, sepic and inverting controller 1.6v v in 42v, current mode control, 100khz to 1mhz programmable operation frequency , msop-12e package related parts 4v to 6v input, 180v output flyback converter sense2 fbx sense1 LT3957A t1 1:10 v in sw gnd rt ss intv cc en/uvlo sync sgnd 37.4k v c 3957a ta05 d1 d2 danger! high voltage! 75k 22 220pf 140k 100khz 4.7f 10v x5r 10nf 0.1f 10k 10nf 100pf 22 15.8k 1.80m c out 68nf 2 v out 180v 15ma v in 4v to 6v c in 100f 6.3v 2 t1: tdk dct15efd-u44s003 c in : grm31cr60j107me39l c out : grm43qr72j683kw01l d1: vishay siliconix gsd2004s dual diode connected in series d2: diodes mmsz5258b ? ? http://www..net/ datasheet pdf - http://www..net/

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